A high level simulator feasible for reliability analysis of VLSI circuits

A high level timing simulator has been developed with emphasis on design-for-reliability of VLSI circuits, in particular digital circuits. It features high speed performance which is at least 100* faster than SPICE for circuit simulation. The input is at the gate-level and so is more suitable for VLSI circuit analysis. A new reliability model is also incorporated in the simulator so that the simulator is feasible for reliability analysis of device or circuit degradation due to the hot carrier effect. Two typical examples for predicting the lifetime of a device or circuit in a VLSI environment are demonstrated.<>