The basis and architecture for the reduction of tones in a sigma-delta DAC

A basis and architecture for a digital-to-analog conversion (DAC) technique that allows a significant, if not complete, reduction of the in-band tones found in single-bit sigma-delta modulators, while easing the component matching requirements compared to conventional multibit architectures, is presented. The architecture uses a combination of coarse and fine quantization levels, which resolves the input data at a rate that is sufficient to keep tones, caused by DC inputs, from occurring in the signal bandwidth. Although a DAC is discussed, it is noted that an analog-to-digital converter (ADC) has similar characteristics. Observations and additional comments relating to the time domain point of view of a sigma-delta converter are offered.<>