Design optimization for deep-submicron CMOS device at low temperature operation

Design optimization for 0.3 mu m channel CMOS technology at liquid-nitrogen temperature. (77 K) is described. The trade-off between circuit performance and reliability of deep submicrometer CMOS devices at low-temperature operation is theoretically and experimentally examined. A simulator has been developed which selects power-supply voltage and process/device parameters for low-temperature operation. Based on the simulated results, design optimization for low-temperature operation has been proposed to determine power-supply voltage and various process and device parameters. This scaling guideline has been applied to a 0.3 mu m CMOS device. Excellent device characteristics and a functional ring oscillator circuit have been obtained at 77 K.<>