Design of a 16 kbit variable threshold Josephson RAM

A 16 kb Josephson RAM (random access memory) has been designed using a miniaturized variable threshold memory cell based on a 2 mu m Nb/Al-oxide/Nb junction technology. By using a novel strip-line structure for the inductance of the superconducting quantum interference device (SQUID) type selection gate, the miniaturized cell occupies 14 mm 28 mu m, just 20% of the area of a previous cell designed with a 3 mu m rule. OR-INVERT type address decoders are constructed with a new 4JL (four-junction logic) gate with a fan-out of four. The whole circuit occupies a 3.1 mm*5.0 mm area. The access time is evaluated to be 475 ps, with a total power dissipation of 7.3 mW/chip. Based on these performance data and data from a previous 1 kb RAM experiment, the prospects for Josephson VLSIs are discussed.<>