VLSI architecture for a convolution-based DCT in residue arithmetic

A new high speed discrete cosine transform (DCT) architecture based on a cyclic convolution and residue arithmetic is introduced. The approach uses the two step DCT algorithm of P. Duhamel and H. H'Mida (1987). The first step is a cyclic convolution. It is followed by a multiplication with a matrix filled with 0 and +or-1. This algorithm is realized in residue arithmetic. Because the residue arithmetic is carry-free and the chosen DCT algorithm allows a hardware implementation with local interconnections and great regularity, the proposed architecture for an 8*8 DCT can reach throughput rates over 150 MSamples/s, which meets the requirements for HDTV applications. The concept has been confirmed by simulations using a hardware description language.<>