VLSI architectures for image processing and address mapping

Explores VLSI architectures for address computation in geometrical mapping problems. The geometric transformation is reviewed and a set of basic transformations is abstracted to be implemented for general image processing. The homogeneous and two-dimensional Cartesian coordinates are employed to represent the transformations, each of which was implemented via an augmented CORDIC as a processing element. Diversified CORDIC schemes such as nonredundant or redundant arithmetic are examined, among which a specific scheme for a processor, utilizing full pipelining at the micro level, is assessed to produce a single-chip VLSI for 50-Mpixel/s applications under the current state-of-the-art MOS technology.<>