Area and latency efficient CORDIC architectures

The authors present hardware solutions with reduced chip area requirements and power dissipation for parallel array or pipeline implementations of the unified algorithm (providing all known CORDIC, or coordinate rotation digital computer, functions) as well as for specialized architectures, supporting a subset of CORDIC functions. The excessive hardware demands of parallel CORDIC architectures are addressed first and modifications to the standard architectures are introduced that reduce the hardware amount by 20% for the unified algorithm, 30% for the rotation mode, and 50% for the vectoring mode. The values are valid for implementations with both redundant and non-redundant adders. The chip area savings and associated power dissipation decrease are accompanied by speedups for implementations with non-redundant adders between 25% (rotation mode) and 50% (vectoring mode) compared with the standard architecture.<>