Digital CMOS VLSI test generation: a divide-and-conquer algorithm

The authors propose a novel test generation procedure for digital CMOS circuits which uses a hierarchical process starting from the external output stage(s) and working toward the external input stage(s). Because this algorithm processes each sub-circuit separately, it can handle an arbitrarily large circuit more effectively than existing methods. Also, the resulting test set from this algorithm covers both gate-level stuck-at faults and transistor-level faults. Thus, this one set of test patterns can be used both during the design procedure and for manufacturing test. The resulting test length and, thus, application time for this method are shown to be significantly smaller than those of existing methods.<>