A chip compiler for rate-optimal multiprocessor schedules

Discusses an integrated circuit chip compiler which is composed of three components: an optimal cyclo-static scheduler, a circuit generator, and the LAGER system. The chip compiler takes an algorithm described by a fully specified flow graph as input, and generates as output a complete integrated circuit chip set which realizes an optimal cyclo-static multiprocessor implementation of the input graph. The cyclo-static scheduler and the LAGER system are preexisting tools. To complete the chip compiler, the authors describe the circuit generator. The major role of the circuit generator is to bridge the gap between the cyclo-static scheduler and LAGER. The authors describe the total system with specific emphasis on the circuit generator, and illustrate the compilation process with a simple example.<>