A 9 Gbit/s bandwidth multiplexer/demultiplexer CMOS chip

A 622-MHz 28:7 multiplexer/demultiplexer (MUX/DEMUX) 0.9- mu m CMOS chip has been fabricated and tested. All inputs/outputs (I/O) communicate using 100 K ECL logic levels and are single-ended. The chip is packaged in a metal QFP (quad flat pack) package and generates less than 80 mV of ground noise when all outputs switch simultaneously. The total power dissipation is 2.5 W. The device has controlled loop-back paths for system diagnostic purposes. Tests show that the chip operates at more than 740 MHz.<
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