Analysis and guidelines for high-speed VLSI system interconnections

A description is given of the modeling and analysis procedures used to generate system-level wiring rules and net delay equations for IBM's 1.0- mu n CMOS standard-cell design system VLSI products. Business rationale, circuit and package models, and analysis methods are reviewed, as is a sample of the result in a midrange processor environment. High-performance single and multichip packages are used in the analysis, as are high-reliability under- and over-voltage specifications. These choices target the analysis for high-cost, high-performance applications.<>