A knowledge-based methodology for designing concurrent error detecting VLSI circuits

The goal of this research is to develop a structured methodology within an applicative framework to automate the design of concurrent error detecting (CED) VLSI circuits. The authors have utilised AI techniques to integrate a model of the design process with domain specific knowledge such as particular CED techniques and analysis algorithms. This paper describes the broad aspects of a prototype CAD tool PROCEDE (PROlog based Concurrent Error Detecting Expert) that is being developed to enable the testing and subsequent refinement of this methodology. The authors focus on strongly fault-secure (SFS) systems. These are a subset of CED systems whose behaviour is highly desirable.<>