A high-speed dynamically reconfigurable 32-bit CMOS adder

A high-speed, compact three-way dynamically reconfigurable 32-bit CMOS adder is reported. The design of this adder uses an enhanced organization for 32-bit carry lookahead and uses an area-speed efficient dynamic circuit technique, called multiple-output domino logic. The reconfigurability is achieved without significant overhead on the basis of these combined techniques. The 248*1454- mu m/sup 2/ adder, fabricated in a standard 0.9- mu m two-level metal CMOS technology, has demonstrated 32-bit addition times of 8.0 ns at 25 degrees C with V/sub DD/=5.0 V.<>