A digital implementation of a best match classifier

A discussion is presented as to why special-purpose chips are needed for useful implementations of algorithms in such applications as pattern recognition and classification. The authors describe one design in particular, the key feature of which is simple arithmetic processors distributed among data storage to minimize data movement. The algorithm performed by the chip is mapped exactly into the silicon and is tailored to the application in a tradeoff of flexibility for speed. The mapping of the algorithm is such that there are never bus conflicts or memory sharing; this allows every computing element to operate at maximum efficiency.<>