Parallel error correction algorithm in RNS VLSI digital circuits

An important problem in real-time DSP (digital signal-processing) systems with highly integrated components is the capability of automatic error detection and correction. The use of residue number arithmetic allows error detection and correction because of its unweighted nature. A single-error-correction procedure is proposed which is based on the use of redundant residue number systems (RRNS) and the base extension operation. The proposed method uses a small decision table and works in parallel mode; therefore it is suitable for high-speed VLSI circuit realization. A parallel architecture which realizes the method is also introduced.<>