Digital approaches to neural network implementation

This paper considers the digital VLSI implementation of neural nets, with particular emphasis on a particular NN; the Multi-layer Perceptron (MLP) trained using the Back Propagation (BP) algorithm(1). After briefly reviewing the basic computational requirements of NN algorithms, the reasons why a digital VLSI implementation might be chosen are presented. A number of possible candidate architectures are described, and some of the design problems that need to be addressed are then discussed. Finally an outline is given of the digital VLSI architecture under development at BTRL, which provides the option of on-chip training using the BP algorithm.<
>