An array processor implementation of the CORDIC algorithm

Of primary importance to the successful implementation of a parallel processor is the transformation of a sequential algorithm into a parallel form. At first sight the CORDIC algorithm exhibits several useful attributes for achieving such a transformation; the hardware is relatively simple and used repetitively, the inter-processing element communication is localised and straightforward and no global communication is required. A potential problem arises however, due to the sequential nature of the z-equation computation. This cannot be implement strictly in a concurrent way as the result from the previous computation is required before the next one may proceed. The implementation described here seeks to circumvent this problem by the use of extensive word-level pipelining within the processing element.<>