Effect of microscale thermal conduction on the packing limit of silicon-on-insulator electronics

It is pointed out that silicon-on-insulator (SOI) electronics have a buried silicon dioxide layer which inhibits device cooling and reduces the thermal packing limit, the largest number of devices per unit substrate area for which the device operating temperature is acceptably low. Thermal analysis yields the packing limit of SOI MOSFET devices in terms of the device power and the limit on the channel temperature. Thermal conduction is microscale if it is significantly reduced by the boundary scattering of heat carriers, electrons in aluminum, and phonons in silicon. If microscale effects are not considered, the packing limit is overpredicted by 22% for a substrate temperature of 300 K and 100% for substrate temperature of 77 K.<>