Fast ECL-to-CMOS and CMOS-to-ECL translators for an 0.8 mu m BiCMOS gate array

Input/output circuits designed to translate from true ECL levels to CMOS levels without bringing a negative supply voltage on the chip are discussed. Using only +5 V and ground eliminates breakdown and parasitic MOSFET problems caused by having both +5 V and -5 V on the chip. These circuits provide an ECL interface to 0.8 mu m BiCMOS gate arrays and are considerably faster than other translators currently available.<>