Simulation considerations for analog-digital ASICs

Problems and issues in the area of design for testability and how to map the outputs from simulation to a tester are presented. These problems and issues are encountered by mixed-signal analog-digital ASIC designers today. Solutions learned from past experience are given. Proper considerations given to the design for testability aspect and the simulation aspect will allow a mixed-signal design to flow smoothly, without delay from design to silicon delivery. Without proper considerations, a design may be delayed significantly due to testability problems or not knowing what to do with some of the simulation input or output stimuli.<>