A solution to mapping an ASIC design hierarchy into an efficient block-place-and-route layout hierarchy

Netpar, a netlist partitioner tool developed to speed up and automate the process of layout partitioning and preparation is described. The Netpar partitioning commands allow the user to quickly convert the netlist into a good layout hierarchy. Instead of recapturing schematics, the user can easily direct Netpar to restructure the netlist for layout compatibility. Additionally, an automatic partitioner is available that attempts to equalize block sizes and minimize interconnect. This implements well-documented and tested algorithms for generating optimally partitioned netlists. Netpar's automatic and manual commands can be used to quickly modify hierarchy to improve design performance, turnaround times, and densities.<>