1 K*128 high-performance, low power configurable CMOS SRAM compiler

A high-density, high-performance, low-power, configurable, fully static RAM compiler is discussed. The compiler can generate different SRAM configurations with a minimum of 128 bits, up to a maximum of 128 K bits. The SRAM has been verified in silicon to have a typical access time of 11 ns (1.0- mu m ASIC process) for a 4 K*16 configuration and is functional from 3.5 V to 7.0 V power supply.<>