A parallel min-cut technique for standard cell placement using a modified Hopfield neural network

The authors present a new min-cut technique for standard cell placement using a modified Hopfield neural network. The neural network has the advantage of a massively parallel architecture, which can drastically reduce computation time in a hardware implementation. It also allows all partitions at a given level of the hierarchical procedure to be performed in parallel, thus overcoming a common drawback of sequential min-cut procedures. The approach has produced very good results on a number of practical standard cell circuits.<>