Parameter selection for digital realisations of neural networks

Many real time applications of multi-layer perceptrons require dedicated specialised hardware. A hardware system is being developed by British Telecom which is primarily aimed at vision applications. Its parallel architecture consists of a linear array of node processors. The node processor is implemented as a custom VLSI chip developed by British Telecom called HANNIBAL (hardware architecture for neural networks, implementing back-propagation algorithm learning) which is fabricated using a sub-micron CMOS process developed by the ESPRIT ACCES project. HANNIBAL supports on-chip weights and back-propagation in fixed-point arithmetic. Both 8-bit and 16-bit weight options are provided. The paper focusses on the techniques used to determine wordlengths and other parameters for this chip.<
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