High speed CMOS chip to chip communication circuit

Communication circuits between chips through transmission lines are demonstrated. In standard packages, a single-output 75- Omega line driver in a 2- mu m CMOS process reaches a data rate of 700 Mb/s, and a differential-output 50- Omega line driver plus a receiver in a 1.2- mu m CMOS process works up to a data rate of 1 Gb/s. By using leadless chip carriers, the 75- Omega line driver in a 1.2- mu m CMOS process gives a maximum data rate of 1.3 Gb/s. These are measured results. The differential driver and receiver should be able to work at a data rate of 1.25 Gb/s with a leadless chip carrier. The impact of packaging on high speed chip to chip communication is discussed.<>