Multiple bus networks based on block designs

Proposes a class of multiple bus networks with O(n) processors and O(n) buses, in which each bus connects to O( square root n) processors and each processor connects to O( square root n) buses. The networks are single-hop: any two processors are connected to exactly one bus. The authors prove that the multiple buses with constant fanout and constant bus loading are the best in terms of bus-time product. For those networks with n processors whose existence is unknown or has been disproved, the authors construct relaxed networks with small skew in bus-loading. The proposed multiple bus networks match well with the multichip module technology.<>