DCT architectures for HDTV

The design of DCT (discrete cosine transform) circuits for HDTV (high-definition television) applications is addressed. Based on previous works on CCIR video image coding, several architectural solutions are presented and then compared. An optimization taking into account the potentials of present-day technologies and progress in arithmetic implementation and architecture makes it possible to implement a real-time DCT for HDTV implementation in roughly 40 mm/sup 2/ (0.8- mu m CMOS).<>