Latched differential FET logic

A new circuit topology is proposed for creating complex logic circuits in GaAs. Latched differential FET logic (LDFL) is a fully differential logic family that provides complex logic function capability, tolerance to threshold voltage variations, and complementary, latched-function outputs. LDFL is capable of performing up to eleven levels of logic in one gate, while still giving excellent performance. LDFL also provides improved noise margins due to the use of bootstrapped loads and significantly reduces the load-to-logic ratioing constraint. A nine-level LDFL gate has a delay of 1.7 ns and a static power dissipation of 4 mW as demonstrated in simulations of 4-bit digital comparator circuits.<>