A GaAs pin-for-pin compatible replacement for the ECL 100474 4 K SRAM

In highest-speed cache memory systems, a RAM whose write cycle time is significantly slower than its read cycle time can pose a significant problem to system designers. To solve this problem, a plug-in replacement for the industry standard 100474 ECL RAM has been designed, and has improved read access time and greatly improved write cycle time. It is designed to operate with no change in performance over a wide range of VEE power supplies, from -4.2 V to -5.7 V. The RAM is processed using a standard 3-layer metal process, FETs with two different pinch-off voltages, and 4-inch GaAs wafers. A low-V/sub p/ FET with a nominal pinch-off of -0.15 V is used in the ramcell's cross-coupled latch and also in the low-power super-buffers in the periphery. A depletion FET with a nominal pinch-off of -0.65 V is used for the ramcell's pass gates and throughout the periphery. To improve yield, both row redundancy and column redundancy are implemented. The RAM has an optional VBB input (previously a no-connect on the 100474) which sets the input threshold for all inputs. If this VBB input is left floating or is tied to VEE, an internal switch connects an internal VBB reference to all the input buffers.<>