An experimental 5-Gb/s 16*16 Si-bipolar crosspoint switch

An experimental 16*16, nonblocking, asynchronous crosspoint switch with a data rate of 5-Gb/s per channel is presented. Implemented in a 0.8- mu m, double-poly, self-aligned Si-bipolar ECL technology, the 3-mm*3-mm chip, featuring a multiplexer-type architecture with a three-device crosspoint cell, demonstrates a nominal data path delay of 420 ps with 12.5-ps RMS jitter and a setup time of 1 ns and dissipates about 4.6 W.<>