SiGe HBT design for CMOS compatible SOI

In this paper, we review the process and layout optimization of thin-film (150nm) SOI SiGe HBTs covering a wide range of f_T-BV_ceo tradeoffs, i.e. from ~150GHz f_T to ~8V BV_ceo. We have shown that a SiGe HBT with bulk-like f_T-BV_ceo trade-off can be built on a CMOS compatible SOI substrate. This HBT can be modularly integrated at low cost (4 masks, < 30 steps) in a 0.13 mum SOI CMOS process (Boissonnet et al.). Anticipated applications range from wireless to high-speed analog circuitry