Advanced device process technology for 0.3 mu m self-aligned bipolar LSIs

A novel method is developed for forming a shallow emitter/base and graft base suitable for 0.3- mu m bipolar LSIs. Fabricated 0.5- mu m U-SICOS (U-groove, isolated sidewall base contact structure) transistors are 44 mu m/sup 2/ in size, and have a cutoff frequency (f/sub T/) of 38 GHz and an ECL (emitter coupled logic) gate delay time of 27 ps. BF/sub 2/ ion-implantation was used to form shallow intrinsic base regions. As diffusion from polysilicon by rapid thermal annealing was used to form a shallow emitter profile. A shallow graft base was formed using an improved self-aligned boron diffusion technique. The reduction of parasitic capacitance improves the performance of advanced bipolar devices.<>