Mixed-signal simulation and test generation

This paper presents the current work that is done in order to simulate analog or mixed-signal tests and then transfer these simulations and their results to the ATE. After having stated the problem, the proposed flow will be reviewed, leading to a more detailed description of the VHDL-AMS simulations, of the STIL-AMS language under definition, as well as to its road map. One of the major decisions taken, a device-centric approach versus a tester-centric approach, will then be explained, before showing some of the actual limitations of the approach. Before concluding, the real case that has been implemented will be described, and some of the debug steps that have been done