A 65 nm Ultra-High-Density Dual-Port SRAM with 0.71um/sup ~/ 8T-Cell for SoC

We propose a new access scheme of synchronous dual-port (DP) SRAM that minimizes area of 8T-DP-cell and keeps cell stability. A priority row decoder circuit and shifted bit-line access scheme eliminates access conflict problem. Using 65nm CMOS technology (hp90), we fabricated 32KB DP-SRAM macros with the proposed scheme. We obtain 0.71mum₂ 8T-DP-cell, which cell size is 1.44times larger than 6T-single-port (SP) cell