An eye detection technique for clock and data recovery applications

An eye detection technique to detect maximum vertical eye opening points for data recovery circuit (CDR) applications and the circuit implementation of an eye detector (ED) are reported in this paper. The ED samples the incoming data to generate the retimed data and produces an error signal indicating whether the sampling point leads or lags the maximum eye opening point, where the lowest BER is expected. The ED is implemented in CMOS 0.18/spl mu/m technology, and its feasibility is confirmed by transistor-level simulations.