Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors

A fully-differential quadrature PLL with common-mode noise immunity has been developed by using a differentially controlled quadrature-VCO (Q-VCO) along with a differential charge-pump (CP). To increase the common-mode rejection ratio (CMRR) of Q-VCO, a simple bias shifting technique was used with accumulation-depletion mode MOS varactors. The measured minimum CMRR of the Q-VCO control gain is more than 30dB and the frequency tuning range is 26.3% around the 2.5GHz center frequency with a 3-bit capacitor bank array. To reduce the overall power consumption, an architectural optimization and an inter-stage impedance matching (ISM) techniques were used in frequency divider circuits. Our frequency synthesizer was fabricated in a 1P6M 0.18/spl mu/m RFCMOS process, and the measured phase noise is -112dBc/Hz at 1MHz offset from the 2.458GHz output frequency while the total PLL current consumption is 8.2mA for 1.8V supply voltage.