A low energy VLSI design of random block interleaver for 3GPP turbo decoding

In this paper hardware architecture for internal random block interleaver compliant with the 3rd Generation Partnership Project (3GPP) turbo decoding is described. The complexity of this algorithm results in other implementations using large memories as address tables. In this implementation real time address computation avoids the use of pre-computed address storage. This greatly reduces the load on the processor and gives significant improvements in area and power. ASIC synthesis results on 0.18 mum CMOS UMC technology demonstrate the efficiency of the proposed VLSI interleaver architecture