A Scheduler Support Unit for Reactive Microprocessors

Efficient scheduling mechanisms are essential for implementing real-time operating systems on embedded microprocessors. Reactive processors provide mechanisms and an instruction set architecture more suitable for dealing with external signals than it is the case with traditional interrupts. By extending the reactive framework further we demonstrate simple and efficient hardwareimplemented scheduling of tasks with static priorities. The scheduler support unit is added to the reactive microprocessor core. The real-time scheduler shows substantial improvement of performance over the conventional approach of using prioritized interrupts.