Efficient Calibration through Statistical Behavioral Modeling of a High-Speed Low-Power ADC

We address the problem of calibrating a flash analog-to-digital converter (ADC) for ultra-wide band energy-constrained receivers. To achieve a superior power efficiency the ADC exploits an unusual comparator architecture that is capable of avoiding the reference ladder, but need threshold calibration for offset compensation. In this work, we present a foreground calibration technique, which aims at reducing the required energy by minimizing the number of clock cycles required for calibration. Optimization is performed relying on a fast and accurate ADC statistical behavioral model, which is also useful to characterize different calibration schemes and provide feedback to the system designer, avoiding expensive electrical simulations. The proposed technique is successfully applied to a 4-bit 90nm CMOS ADC prototype, obtaining INL< 0.15LSB, DNL<0.2LSB and 3.7-ENOB at 1.25GS/s at the expense of only 15.17nJ ADC energy