VHDL Code Automatic Generator for Systolic Arrays

Systolic arrays speed up scientific computations with inherent parallelization, by exploiting massive data pipeline parallelism. In addition, they include short and problem-size independent signal paths, predictable performance, scalability, and simple design and test. In this paper, a server-based software tool for the automatic generation of VHDL code describing systolic arrays topologies is presented. Input parameters of the tool are several essential factors for the architectural description of systolic arrays (SA), like the interconnection topology of the systolic array, i.e., linear, mesh or hex-connected, the size of the systolic array, i.e., the number of the processing elements (PE) in each dimension, the function of the PE, i.e., the relation between the output and the input ports of every PE and finally the bitlength of PE ports, i.e., the data word size of every port