A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word*1 b/1 M word*4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm*8.77 mm. Memory cell size is 5.8 mu m*3.2 mu m. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55- mu m BiCMOS process technology with a triple-well structure.<>