High density tantalum pentoxide decoupling capacitors

High-performance ICs require extremely low impedance power distribution. The low voltage, high current requirements of these devices must be provided by decoupling capacitors very close to the IC. Currently this decoupling is provided by discrete surface mount capacitors with relatively high parasitic inductance, requiring many devices in parallel to provide low impedance at high frequencies. Thin film, large area Ta₂O₅ dielectric capacitors exhibit very low parasitic inductance, but have been limited in capacitance density to -100 nF/cm₂ for single layer devices. Multilayer thin film capacitors can substantially increase the available capacitance. These multilayer thin film capacitors can be fabricated in a variety of ways, allowing them to be embedded between FR-4 layers, under ICs, or even embedded in IC packages. Last year at ECTC we described the initial results of two-layer capacitors fabricated on silicon. These devices had two dielectric layers and three copper plates. Now we have extended the technology to three dielectric layers, and have fabricated devices with dielectrics as thin as 1000 Aring, to yield a capacitance density of .6 muF/cm². Capacitors are fabricated on silicon wafers by sputtering a metal plate topped with tantalum, and then wet anodizing the tantalum layer. The process is repeated to create a multilayer stack; then the stack is patterned from top to bottom by successive lithographic and etching steps. The paper describes the process in detail. Detailed electrical properties for the resulting devices, such as capacitance density, leakage current, breakdown voltage, and impedance will be presented. Using the three-layer process, we have fabricated devices for inclusion in a 3-D electronic assembly for a DARPA program, and these devices are described. Screening and test methods to ensure device reliability are discussed