A dual-port SRAM compiler for 0.8- mu m 100 K BiCMOS gate arrays

A 6-ns dual-port BiCMOS SRAM compiler has been designed for a 0.8- mu m 100K sea-of-gates array. A novel merged bipolar/CMOS memory bit architecture incorporating local interconnect utilizes all base cell transistor sites. Through the use of local interconnect in the memory bit cell, high memory density is achieved. Increased speed is obtained by using bipolar transistors in the memory bit cell, address decoders, and word line drivers. Compiler software can generate RAM instances up to 2K words and 8K total bits.<>