Electrical characteristics of 25 mil pitch JEDEC PQFP surface mount lead frames for multichip modules

The electrical characteristics of the leadframe used to form the JEDEC standard 25-mil-pitch PQFP (POLYHIC quad flat pack) outline package are examined. The characteristic impedance is computed and three models of the leadframe pins are created for each ground configuration case for both isolated and coupled pairs of pins. Crosstalk between adjacent pins has been simulated and measured as a function of signal risetime. The risetime degradation of signals transmitted through the leadframe pins has been simulated and measured. These data have been used to estimate a conservative upper limit for clock and data rate capability of this leadframe. The POLYHIC PQFP outline package is shown to be a multi-gigabit-per-second package.<>