Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n+/p+Poly Top/Bottom Gate

This paper reports the gate-misalignment-effect related capacitance behavior of a 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n⁺p⁺poly top/bottom gate. Based on the 2D simulation result, with the gate misalignment, the sudden fall in the gate-drain/source capacitance (CGD/CGS) of the device at VG=0.5V is mitigated due to the reduced hole accumulation/ depletion in the bottom channel controlled by the p⁺bottom gate with the increased fringing electric field effect.