Predictive Line Buffer: A Fast, Energy Efficient Cache Architecture

Two of the most important factors in the design of any processor are speed and energy consumption. Depending on the application, and the processor type, generally one of these two factors will be more important than the other. In this paper, we propose a new cache architecture. Our proposed architecture does not require any changes to the processor architecture, it only assume the existence of a BTB, and it adds few gates and multiplexers for the prediction mechanism. By using Simplescalar simulator, CACTI 3.2 power simulator, and SPEC2000, Mediabench, and Mibench, we tested our proposed architecture using a wide variety of the programs in these three benchmarks. Our results show that our proposed architecture consumes less energy, and have better memory access time, than many existing cache architecture