An adaptive analog-to-digital converter based on low-power dynamic latch comparator

This paper presents a low power adaptive flash A/D converter, which enables the dynamic trade-off between resolution and power consumption. Instead of using the traditional amp lifter-chain type comparators, the dynamic latch comparators are applied in order to achieve low power dissipation. Furthermore, the non-OP Amp architecture provides the design with ability to be fully compatible with standard digital VLSI process. Lower supply voltage and less mask steps is hence achievable. The A/D converter was designed with 0.5-/spl mu/m CMOS technology and capable of operating up to 250 MHz with 5-bit, 6-bit and 7-bit precision. Benefiting from 50% less power consumption than conventional designs and exponentially reduced power with linearly reduced resolution, the design is applicable to wireless applications and various low power portable devices.