Multiple constrained folding of programmable logic arrays by simulated annealing

The PLA (programmable logic array) topological optimization problem is dealt with using folding techniques. Multiple unconstrained column folding is considered and this problem is solved using the simulated annealing algorithm. This algorithm is then extended to handle several types of constraints. Multiple constrained folding problems are solved using bipartite graphs. This allows the system to move only into a set of valid solutions. Comments are made concerning the experimental results obtained in the algorithm execution.<>