A low-voltage RF amplifier using parallel triode MOSFET linearizing technique

A low-voltage CMOS radio frequency amplifier using linearizing technique is presented in this paper. In this circuit, a parallel MOSFET in the triode region was used to boost the linearity. The circuit was fabricated with SMIC 0.18 /spl mu/m CMOS process. Measurement shows that the input-referred 3rd-order intercept point (IIP/sub 3/) was improved by about 5 dB with little performances penalty.