A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver

A frequency synthesizer applied to 10/100 Base-T Ethernet transceiver is described. It can work in 10Mbps or 100Mbps mode adaptively and convert from one mode to another freely. The circuit can meet both requirements of transmitter on rising/falling time and receiver on CDR so that the additional power and area are saved. Under some testing circumstance, G of voltage control oscillator jitter/sub cycle-cycle/ is only 22ps with G of reference clock jitter/sub cycle-cycle/ 25ps (Herzel and Razavi, 1997). The testing result proves that the frequency synthesizer has good processing stability and rejection to noises. It works well for transmitter and receiver. The circuit is designed with SMIC 0.35/spl mu/m standard CMOS technology and the power supply is 3.3V.